Semiconductor wafers are typically fabricated using photolithography, which is adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive toward smaller, more highly integrated circuit designs. After each layer of the circuit is etched on the wafer, an oxide layer is put down as the base for the next layer. Each layer of the circuit can create roughness and waviness to the wafer that is preferably removed before depositing the next circuit layer. For many semiconductor applications the chemical mechanical processing (“CMP”) is customized for each layer. A change in a single processing parameter, such as for example, pad design, slurry formulation, or pressure applied by the pad, can require the entire CMP process to be redesigned and recertified.
Magnetic media have similarly stringent planarization requirements as data densities approach 1 Terabyte/inch2 (1 Tbit/in2) and beyond, especially on bit patterned media and discrete track media, such as illustrated in U.S. Pat. Publication 2009/0067082. FIGS. 1 and 2 illustrate the shape of bits formed by etching, such as ion milling or reactive etching. Note that the tops of the bits are rounded, leading to head media spacing loss, roughness at the rounded areas, and magnetic damage due to etching of magnetic materials. Such bits are not viable for magnetic recording. The uneven material increases head media spacing and potential damage to the diamond-like-carbon overcoats. CMP processes have proven inadequate to achieving smooth and flat tops both before and after magnetic material deposition.
CMP is currently the primary approach to planarizing wafers, semiconductors, optical components, magnetic media for hard disk drives, and bit patterned or discrete track media (collectively “substrates”). CMP uses pads to press sub-micron sized particles suspended in the slurry against the surface of the substrate. The nature of the material removal varies with the hardness of the CMP pad. Soft CMP pads conform to the nanotopography and tend to remove material generally uniformly from the entire surface. Hard CMP pads conform less to the nanotopography and therefore remove more material from the peaks or high spots on the surface and less material from low spots.
Traditionally, soft CMP pads have been used to remove a uniform surface layer, such as removing a uniform oxide layer on a semiconductor device. Polishing a substrate with a soft pad also transfers various features from the polishing pad to the substrate. Roughness and waviness is typically caused by uneven pressure applied by the pad during the polishing process. The uneven pressure can be caused by the soft pad topography, the run out of the moving components, or the machined imperfections transferred to the pads. Run-out is the result of larger pressures at the edges of the substrate due to deformation of the soft pad. Soft pad polishing of heterogeneous layered materials, such as semiconductor devices, causes differential removal and damage to the electrical devices.
A CMP pad is generally of a polyurethane or other flexible organic polymer. The particular characteristics of the CMP pad such as hardness, porosity, and rigidity, must be taken into account when developing a particular CMP process for processing of a particular substrate. Unfortunately, wear, hardness, uneven distribution of abrasive particles, and other characteristics of the CMP pad may change over the course of a given CMP process. This is due in part to water absorption as the CMP pad takes up some of the aqueous slurry when encountered at the wafer surface during CMP. This sponge-like behavior of the CMP pad leads to alteration of CMP pad characteristics, notably at the surface of the CMP pad. Debris coming from the substrate and abrasive particles can also accumulate in the pad surface. This accumulation causes a “glazing” or hardening of the top of the pad, thus making the pad less able to hold the abrasive particles of the slurry and decreasing the pad's overall polishing performance. Further, with many pads the pores used to hold the slurry become clogged, and the overall asperity of the pad's polishing surface becomes depressed and matted.
Shortcomings of current CMP processes affect other aspects of substrate processing as well. The sub-micron particles used in CMP tend to agglomerate and strongly adhere to each other and to the substrate, resulting in nano-scale surface defects. Van der Waals forces create a very strong bond between the surface debris and the substrate. Once surface debris form on a substrate it is very difficult to effectively remove them using conventional cleaning methods. Various methods are known in the art for removing surface debris from substrates after CMP, such as disclosed in U.S. Pat. Nos. 4,980,536; 5,099,557; 5,024,968; 6,805,137 (Bailey); U.S. Pat. No. 5,849,135 (Selwyn); U.S. Pat. No. 7,469,443 (Liou); U.S. Pat. No. 6,092,253 (Moinpour et al.); U.S. Pat. No. 6,334,229 (Moinpour et al.); U.S. Pat. No. 6,875,086 (Golzarian et al.); U.S. Pat. No. 7,185,384 (Sun et al.); and U.S. Patent Publication Nos. 2004/0040575 (Tregub et al.); and 2005/0287032 (Tregub et al.), all of which are incorporated by reference, but have proven inadequate for the next generation semiconductors and magnetic media.
Current processing of substrates for semiconductor devices and magnetic media treats uniform surface layer reduction, planarization to remove waviness, and cleaning as three separate disciplines. The incremental improvements in each of these disciplines have not kept pace with the shrinking feature size of features demanded by the electronics industry.